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| 19-3789; Rev 0; 8/05 +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode General Description The MAX4822-MAX4825 8-channel relay drivers offer built-in kickback protection and drive +3V/+5V nonlatching or dual-coil-latching relays. Each independent open-drain output features a 2.7 (typ) on-resistance and is guaranteed to sink 70mA (min) of load current. These devices consume less than 300A (max) quiescent current and have 1A output off-leakage current. A Zener-kickback-protection circuit significantly reduces recovery time in applications where switching speed is critical. The MAX4822/MAX4824 feature a unique power-save mode where the relay current, after activation, can be reduced to a level just above the relay hold-current threshold. This mode keeps the relay activated while significantly reducing the power consumption. The MAX4822/MAX4823 feature a 10MHz SPITM-/ QSPITM-/MICROWIRETM-compatible serial interface. Input data is shifted into a shift register and latched to the outputs when CS transitions from low to high. Each data bit in the shift register corresponds to a specific output, allowing independent control of all outputs. The MAX4824/MAX4825 feature a 4-bit parallel-input interface. The first 3 bits (A0, A1, A2) determine the output address, and the fourth bit (LVL) determines whether the selected output is switched on or off. Data is latched to the outputs when CS transitions from low to high. The MAX4822-MAX4825 feature separate set and reset functions, allowing turn-on or turn-off of all outputs simultaneously with a single control line. Built-in hysteresis (Schmidt trigger) on all digital inputs allows these devices to be used with slow-rising and falling signals, such as those from optocouplers or RC powerup initialization circuits. The MAX4822-MAX4825 are available in space-saving 4mm x 4mm, 20-pin thin QFN packages. They are specified over the -40C to +85C extended temperature range. Features Built-In Zener Kickback Protection for Fast Recovery Programmable Power-Save Mode Reduces Relay Power Consumption (MAX4822/MAX4824) 10MHz SPI-/QSPI-/MICROWIRE-Compatible Serial Interface Eight Independent Output Channels Drive +3V and +5V Relays Guaranteed 70mA (min) Coil Drive Current Guaranteed 5 (max) RON SET / RESET Functions to Turn On/Off All Outputs Simultaneously Serial Digital Output for Daisy Chaining Optional Parallel Interface (MAX4824/MAX4825) Low 300A (max) Quiescent Supply Current Space-Saving, 4mm x 4mm, 20-Pin TQFN Package MAX4822-MAX4825 Ordering Information PART MAX4822ETP MAX4823ETP MAX4824ETP MAX4825ETP TEMP RANGE PINPACKAGE PACKAGE CODE T2044-3 T2044-3 T2044-3 T2044-3 -40C to +85C 20 TQFN-EP* -40C to +85C 20 TQFN-EP* -40C to +85C 20 TQFN-EP* -40C to +85C 20 TQFN-EP* *For maximum heat dissipation, packages have an exposed pad (EP) on the bottom. Solder exposed pad to GND. Applications ATE Equipment DSL Redundancy Protection (ADSL/VDSL/HDSL) T1/E1 Redundancy Protection T3/E3 Redundancy Protection Industrial Equipment Test Equipment (Oscilloscopes, Spectrum Analyzers) SPI is a trademark of Motorola, Inc. QSPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. PART MAX4822 MAX4823 MAX4824 MAX4825 Serial Serial Parallel Parallel Selector Guide INTERFACE POWER SAVE Yes No Yes No Pin Configurations appear at end of data sheet. 1 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode MAX4822-MAX4825 ABSOLUTE MAXIMUM RATINGS VCC ........................................................................-0.3V to +6.0V OUT_ ......................................................................-0.3V to +11V CS, SCLK, DIN, SET, RESET, A0, A1, A2, LVL......-0.3V to +6.0V DOUT..........................................................-0.3V to (VCC + 0.3V) PSAVE ........................................................-0.3V to (VCC + 0.3V) Continuous OUT_ Current (all outputs turned on) ............150mA Continuous OUT_ Current (single output turned on) ........300mA Continuous Power Dissipation (TA = +70C) 20-Lead Thin QFN (derate 16.9mW/C above +70C) ..1350mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Soldering Temperature (10s) ...........................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 2.7V, TA = +25C, unless otherwise noted.) (Note 1) PARAMETER Operating Voltage Quiescent Current Dynamic Supply Current Thermal Shutdown Power-On Reset Power-On Reset Hysteresis DIGITAL INPUTS (SCLK, DIN, CS, LVL, A0, A1, A2, RESET, SET) Input Logic-High Voltage Input Logic-Low Voltage Input Logic Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUT (DOUT) DOUT Low Voltage DOUT High Voltage VOL VOH ISINK = 6mA ISOURCE = 0.5mA VCC 0.5 0.4 V V VIH VIL VHYST ILEAK CIN Input voltages = 0 or 5.5V -1.0 VCC = 2.7V to 3.6V VCC = 4.2V to 5.5V VCC = 2.7V to 3.6V VCC = 4.2V to 5.5V 150 +0.01 5 +1.0 2.0 2.4 0.6 0.8 V V mV A pF SYMBOL VCC ICC ID IOUT_ = 0, logic inputs = 0 or VCC fSCLK =10MHz, CDOUT = 50pF VCC = 3.6V VCC = 5.5V VCC = 3.6V VCC = 5.5V CONDITIONS MIN 2.3 160 180 1.2 1.6 +130 +150 0.6 1.2 140 2.0 TYP MAX 5.5 300 300 UNITS V A mA C V mV Power-save disable threshold (Note 2) Output disable threshold (Note 3) Transform from high voltage to low voltage 2 _______________________________________________________________________________________ +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode ELECTRICAL CHARACTERISTICS (continued) (VCC = +2.7V to +5.5V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 2.7V, TA = +25C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN 0.65 x VCC 0.55 x VCC 0.45 x VCC 0.35 x VCC 0.25 x VCC 0.15 x VCC 0.05 x VCC 0.35 x VCC -1 7.0 9 TYP 0.7 x . VCC 0.6 x VCC 0.5 x VCC 0.4 x VCC 0.3 x VCC 0.2 x VCC 0.1.x VCC 0.4 x VCC 2.7 MAX 0.75 x VCC 0.65 x VCC 0.55 x VCC 0.45 x VCC 0.35 x VCC 0.25 x VCC 0.15 x VCC 0.45 x VCC 5.0 +1 10.5 V A V V UNITS MAX4822-MAX4825 RELAY OUTPUT DRIVERS (OUT1-OUT8) PS = 001 PS = 010 PS = 011 OUT_ Drive Voltage, Power-Save On (MAX4822) VOUTPS_ VCC = 2.7V (Note 4) PS = 100 PS = 101 PS = 110 PS = 111 OUT_ Drive Voltage, Power-Save On (MAX4824) OUT_ On-Resistance OUT_ Off-Leakage Current Zener Clamping Voltage SPI TIMING (MAX4822/MAX4823) Turn-On Time (OUT_) Turn-Off Time (OUT_) SCLK Frequency Cycle Time CS Fall-to-SCLK Rise Setup CS Rise-to-SCLK Hold SCLK High Time SCLK Low Time Data Setup Time tON tOFF fSCLK tCH + tCL tCSS tCSH tCH tCL tDS From rising edge of CS, RL = 50, CL = 50pF From rising edge of CS, RL = 50, CL = 50pF 0 100 50 50 40 40 20 1.0 3.0 10 s s MHz ns ns ns ns ns ns VOUTPS_ RON ILEAK VCLAMP VCC = 2.7V (Note 4) VCC = 2.7V, IOUT_ = 70mA VOUT_ = VCC, all outputs off IOUT_ = 70mA (Note 5) _______________________________________________________________________________________ 3 +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode MAX4822-MAX4825 ELECTRICAL CHARACTERISTICS (continued) (VCC = +2.7V to +5.5V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 2.7V, TA = +25C, unless otherwise noted.) (Note 1) PARAMETER Data Hold Time SCLK Fall to DOUT Valid Rise Time (DIN, SCLK, CS, SET, RESET) Fall Time (DIN, SCLK, CS, RESET, SET) RESET Minimum Pulse Width SET Minimum Pulse Width CS Minimum Pulse Width SYMBOL tDH tDO tSCR tSCF tRW tSW tCSW From rising edge of CS, RL = 50, CL = 50pF From rising edge of CS, RL = 50, CL = 50pF 20 0 20 0 20% of VCC to 70% of VCC, CL = 50pF (Note 6) 20% of VCC to 70% of VCC, CL = 50pF (Note 6) 70 70 40 Variation from typical value, CL = 100nF (Note 7) 2 2 50% of SCLK to (VIH, VIL of DIN), CL = 50pF 20% of VCC to 70% of VCC, CL = 50pF (Note 6) 20% of VCC to 70% of VCC, CL = 50pF (Note 6) 70 70 40 CONDITIONS MIN 0 17 28 2 2 TYP MAX UNITS ns ns s s ns ns ns PARALLEL TIMING (MAX4824/MAX4825) Turn-On Time Turn-Off Time LVL Setup Time LVL Hold Time Address to CS Setup Time Address to CS Hold Time Rise Time (A2, A1, A0, LVL) Fall Time (A2, A1, A0, LVL) RESET Pulse Width SET Pulse Width CS Minimum Pulse Width tON tOFF tLS tLH tAS tAH tSCR tSCF tRW tSW tCSW 1 3 s s ns ns ns ns s s ns ns ns POWER-SAVE TIMING (MAX4822/MAX4824) Power-Save Delay Time Minimum PSAVE Low Time to Power-Save Reset tPS tPSR 1.6 3.2 2 5.4 3.5 ms ms Note 1: Note 2: Note 3: Note 4: Note 5: Specifications at -40C are guaranteed by design and not production tested. Thermal shutdown disables power save from all channels to reduce power dissipation inside the device. Thermal shutdown turns off all channels. The circuit can set the output voltage in power-save mode only if IOUT x RON < VOUTP. After relay turn-off, inductive kickback can momentarily cause the OUT_ voltage to exceed VCC. This is considered part of normal operation and does not damage the device. Note 6: Guaranteed by design. Note 7: For other capacitance values, use the equation tPS = 32 x C. 4 _______________________________________________________________________________________ +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode MAX4822-MAX4825 Typical Operating Characteristics (VCC = 3.3V, TA = +25C, unless otherwise noted.) QUIESCENT SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX4822-25 toc01 QUIESCENT SUPPLY CURRENT vs. TEMPERATURE MAX4822-25 toc02 DYNAMIC SUPPLY CURRENT vs. FREQUENCY 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 VCC = 3.6V VCC = 5.5V CDOUT = 50pF MAX4822-25 toc03 180 ALL CHANNELS OFF 175 SUPPLY CURRENT (A) 170 165 160 155 150 145 140 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 200 190 180 SUPPLY CURRENT (A) 170 160 150 140 130 120 110 100 VCC = 2.3V VCC = 3.3V VCC = 5.0V VCC = 5.5V 2.00 DYNAMIC SUPPLY CURRENT (mA) 5.5 -40 -15 10 35 60 85 1 2 3 4 5 6 7 8 9 10 SUPPLY VOLTAGE (V) TEMPERATURE (C) FREQUENCY (MHz) QUIESCENT SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE MAX4822-25 toc04 ON-RESISTANCE vs. SUPPLY VOLTAGE MAX4822-25 toc05 ON-RESISTANCE vs. TEMPERATURE IOUT-SINK = 70mA 3.5 VCC = 2.3V VCC = 3.3V MAX4822-25 toc06 1100 1000 900 SUPPLY CURRENT (A) 800 700 600 500 400 300 200 100 0 0 1 2 3.50 IOUT_SINK = 70mA 3.25 3.00 RON () 2.75 2.50 2.25 2.00 ALL LOGIC INPUTS CONNECTED 4.0 VCC = 5.5V RON () 3.0 VCC = 3.3V 2.5 2.0 1.75 1.50 3 4 5 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 LOGIC-INPUT VOLTAGE (V) SUPPLY VOLTAGE (V) 1.5 -40 -15 10 VCC = 5.0V 35 60 85 VCC = 5.5V TEMPERATURE (C) POWER-ON RESET VOLTAGE vs. TEMPERATURE 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 -40 -15 10 35 60 TEMPERATURE (C) MAX4822-25 toc07 OUTPUT OFF-LEAKAGE CURRENT vs. SUPPLY VOLTAGE MAX4822-25 toc08 OUTPUT OFF-LEAKAGE CURRENT vs. TEMPERATURE MAX4822-25 toc09 6 5 OUTPUT OFF-LEAKAGE (pA) 4 3 2 1 0 10 POWER-ON RESET VOLTAGE (V) OUTPUT OFF-LEAKAGE (nA) 1 2.3V, 3.3V, 5.0V, AND 5.5V 0.1 0.01 0.001 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 -40 -15 10 35 60 85 SUPPLY VOLTAGE (V) TEMPERATURE (C) 85 _______________________________________________________________________________________ 5 +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode MAX4822-MAX4825 Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25C, unless otherwise noted.) OUT_ TURN-ON DELAY TIME vs. SUPPLY VOLTAGE MAX4822-25 toc10 OUT_ TURN-OFF DELAY TIME vs. SUPPLY VOLTAGE MAX4822-25 toc11 INPUT-LOGIC THRESHOLD vs. SUPPLY VOLTAGE 2.0 INPUT-LOGIC THRESHOLD (V) 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 MAX4822-25 toc12 140 120 ION DELAY TIME (ns) 100 80 60 40 20 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 1600 1400 IOFF DELAY TIME (ns) 1200 1000 800 600 400 2.1 5.5 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) BACK EMF CLAMPING WITH STANDARD 3V RELAY VCC = 3.3V MAX4822-25 toc13 POWER-SAVE DELAY TIME vs. CAPACITANCE VCC = 3.3V 35 30 25 tPS (ms) 20 15 10 MAX4822-25 toc14 40 CS 5V/div 0V VOUT 2V/div 0V 5 0 100s/div 0 200 400 600 800 1000 CAPACITANCE (nF) POWER-SAVE DELAY TIME vs. SUPPLY VOLTAGE MAX4822-25 toc15 OUTPUT VOLTAGE vs. OUTPUT CURRENT IN POWER-SAVE MODE (PSAVE REGISTER = 111) MAX4822 toc16 4.00 3.95 3.90 3.85 tPS (ms) 3.80 3.75 3.70 3.65 3.60 3.55 3.50 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 CPSAVE = 0.1F 0.8 0.7 OUTPUT VOLTAGE (V) 0.6 0.5 0.4 0.3 5.5 0 50 100 150 200 250 300 SUPPLY VOLTAGE (V) OUTPUT CURRENT (mA) 6 _______________________________________________________________________________________ +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode MAX4822/MAX4823 Pin Description PIN MAX4822 MAX4823 NAME FUNCTION Reset Input. Drive RESET low to clear all latches and registers (all outputs are high impedance). RESET overrides all other inputs. If RESET and SET are pulled low at the same time, then RESET takes precedence. Chip-Select Input. Drive CS low to select the device. When CS is low, data at DIN is clocked into the shift register on SCLK's rising edge. Drive CS from low to high to latch the data to the registers and activate the relay outputs. Serial Data Input Serial Clock Input Serial Data Output. DOUT is the output of the shift register. DOUT can be used to daisychain multiple MAX4822/MAX4823 devices. The data at DOUT appears synchronous to SCLK's falling edge. No Connection. Not internally connected. Ground Open-Drain Output 8. Connect OUT8 to the low side of a relay coil. This output is pulled to PGND when activated, but otherwise is high impedance. Open-Drain Output 7. Connect OUT7 to the low side of a relay coil. This output is pulled to PGND when activated, but otherwise is high impedance. Power Ground. PGND is a return for the output sinks. Connect PGND pins together and to GND. Open-Drain Output 6. Connect OUT6 to the low side of a relay coil. This output is pulled to PGND when activated, but otherwise is high impedance. Open-Drain Output 5. Connect OUT5 to the low side of a relay coil. This output is pulled to PGND when activated, but otherwise is high impedance. Power-Save Control. Connect a timing capacitor from PSAVE to ground. The capacitor value determines power-save timing as explained under the Applications Information section. PSAVE can also be driven externally to control power-save mode asynchronously. When asserted high, PSAVE reduces the current to all active outputs as determined by the Power-Save Configuration Register (see Figure 1). To disable powersave mode in all channels, drive PSAVE low for at least 3ms after the last output setting. Open-Drain Output 4. Connect OUT4 to the low side of a relay coil. This output is pulled to PGND when activated, but otherwise is high impedance. Open-Drain Output 3. Connect OUT3 to the low side of a relay coil. This output is pulled to PGND when activated, but otherwise is high impedance. Open-Drain Output 2. Connect OUT2 to the low side of a relay coil. This output is pulled to PGND when activated, but otherwise is high impedance. Open-Drain Output 1. Connect OUT1 to the low side of a relay coil. This output is pulled to PGND when activated, but otherwise is high impedance. MAX4822-MAX4825 1 1 RESET 2 3 4 5 6 7 8 9 10, 16 11 12 2 3 4 5 6, 13 7 8 9 10, 16 11 12 CS DIN SCLK DOUT N.C. GND OUT8 OUT7 PGND OUT6 OUT5 13 -- PSAVE 14 15 17 18 14 15 17 18 OUT4 OUT3 OUT2 OUT1 _______________________________________________________________________________________ 7 +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode MAX4822-MAX4825 MAX4822/MAX4823 Pin Description (continued) PIN MAX4822 19 20 EP MAX4823 19 20 EP NAME VCC SET EP FUNCTION Input Supply Voltage. Bypass VCC to GND with a 0.1F capacitor. Set Input. Drive SET low to set all latches and registers high (all outputs are low impedance). SET overrides all parallel and serial control inputs. RESET overrides SET under all conditions. Exposed Pad. Connect exposed paddle to GND. MAX4824/MAX4825 Pin Description PIN MAX4824 MAX4825 NAME FUNCTION Reset Input. Drive RESET low to clear all latches and registers (all outputs are high impedance). RESET overrides all other inputs. If RESET and SET are pulled low at the same time, then RESET takes precedence. Chip-Select Input. Drive CS low to select the device. The CS falling edge latches the output address (A0, A1, A2). The CS rising edge latches level data (LVL). Level Input. LVL determines whether the selected address is switched on or off. Logichigh on LVL switches on the addressed output. A logic-low on LVL switches off the addressed output. Digital Address 0 Input. (See Figure 3 for address mapping.) Digital Address 1 Input. (See Figure 3 for address mapping.) Digital Address 2 Input. (See Figure 3 for address mapping.) Ground Open-Drain Output 8. Connect OUT8 to the low side of a relay coil. This output is pulled to PGND when activated, but otherwise is high impedance. Open-Drain Output 7. Connect OUT7 to the low side of a relay coil. This output is pulled to PGND when activated, but otherwise is high impedance. Power Ground. PGND is a return for the output sinks. Connect PGND pins together and to GND. Open-Drain Output 6. Connect OUT6 to the low side of a relay coil. This output is pulled to PGND when activated, but otherwise is high impedance. Open-Drain Output 5. Connect OUT5 to the low side of a relay coil. This output is pulled to PGND when activated, but otherwise is high impedance. 1 1 RESET 2 2 CS 3 4 5 6 7 8 9 10, 16 11 12 3 4 5 6 7 8 9 10, 16 11 12 LVL A0 A1 A2 GND OUT8 OUT7 PGND OUT6 OUT5 8 _______________________________________________________________________________________ +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode MAX4824/MAX4825 Pin Description (continued) PIN MAX4824 MAX4825 NAME FUNCTION Power-Save Control. Connect a timing capacitor from PSAVE to ground. The capacitor value determines power-save timing as explained under the Applications Information section. PSAVE can also be driven externally to control power-save mode asynchronously. When PSAVE is asserted high, the current through the coils is reduced to 60% of the initial nominal current value. To disable power-save mode in all channels, drive PSAVE low for at least 3ms after last output setting. Open-Drain Output 4. Connect OUT4 to the low side of a relay coil. This output is pulled to PGND when activated, but otherwise is high impedance. Open-Drain Output 3. Connect OUT3 to the low side of a relay coil. This output is pulled to PGND when activated, but otherwise is high impedance. Open-Drain Output 2. Connect OUT2 to the low side of a relay coil. This output is pulled to PGND when activated, but otherwise is high impedance. Open-Drain Output 1. Connect OUT1 to the low side of a relay coil. This output is pulled to PGND when activated, but otherwise is high impedance. Input Supply Voltage. Bypass VCC to GND with a 0.1F capacitor. Set Input. Drive SET low to set all latches and registers high (all outputs are low impedance). SET overrides all parallel and serial control inputs. RESET overrides SET under all conditions. No Connection. Not internally connected. Exposed Pad. Connect exposed paddle to ground. MAX4822-MAX4825 13 -- PSAVE 14 15 17 18 19 20 -- EP 14 15 17 18 19 20 13 EP OUT4 OUT3 OUT2 OUT1 VCC SET N.C. EP Detailed Description Serial Interface (MAX4822/MAX4823) Depending on the MAX4822/MAX4823 device, the serial interface can be controlled by either 8- or 16-bit words as depicted in Figures 1 and 2. The MAX4823 does not support power-save mode, so the serial interface consists of an 8-bit-only shift register for faster control. The MAX4822 consists of a 16-bit shift register and parallel latch controlled by SCLK and CS. The input to the shift register is a 16-bit word. In the MAX4822, the first 8 bits determine the register address and are followed by 8 bits of data as depicted in Figure 1. Bit A7 corresponds to the MSB of the 8-bit register address in Figure 1, while bit D7 corresponds to the MSB of the 8 bits of data in the same Figure 1. The MAX4823 consists of an 8-bit shift register and parallel latch controlled by SCLK and CS. The input to the shift register is an 8-bit word. Each data bit controls one of the eight outputs, with the most significant bit (D7) corresponding to OUT8, and the least significant bit (D0) corresponding to OUT1 (see Figure 2). _______________________________________________________________________________________ 9 +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode MAX4822-MAX4825 ADDRESS [A7...A0] 00h 01h Serial-Input Address Map D7 OUT8 D6 OUT7 D5 OUT6 D4 OUT5 D3 OUT4 D2 OUT3 D1 OUT2 D0 OUT1 ACTIVE REGISTER Output Control Register--OUTR P o we r - S a ve C o n fig u r a tio n Re gist e r --P S MSB LSB Output Control Register--OUTR (Address = 00h) Note: Setting DN to logic 1 turns on output OUTN+1. Setting DN to logic 0, turns off OUTN+1. Example: Setting D2 = 1 turns on OUT3. D7 X D6 X D5 X D4 X D3 X D2 PS0 D1 PS1 D0 PS2 LSB MSB Power-Save Configuration Register--PS (Address= 01h) PS0 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS2 0 1 0 1 0 1 0 1 POWER-SAVE CONFIGURATION Power-save is disabled (Default Operation) Power-save is enabled. VOUT set to 70% of VCC, typical after tPS ms (see Note 1), causes IOUT_ to be reduced to approximately 30%, typical after tPS ms. Power-save is enabled. VOUT set to 60% of VCC, typical after tPS ms (see Note 1), causes IOUT_ to be reduced to approximately 40%, typical after tPS ms. Power-save is enabled. VOUT set to 50% of VCC, typical after tPS ms (see Note 1), causes IOUT_ to be reduced to approximately 50%, typical after tPS ms. Power-save is enabled. VOUT set to 40% of VCC, typical after tPS ms (see Note 1), causes IOUT_ to be reduced to approximately 60%, typical after tPS ms. Power-save is enabled. VOUT set to 30% of VCC, typical after tPS ms (see Note 1), causes IOUT_ to be reduced to approximately 70%, typical after tPS ms. Power-save is enabled. VOUT set to 20% of VCC, typical after tPS ms (see Note 1), causes IOUT_ to be reduced to approximately 80%, typical after tPS ms. Power-save is enabled. VOUT set to 10% of VCC, typical after tPS ms (see Note 1), causes IOUT_ to be reduced to approximately 90%, typical after tPS ms. Power-Save Configuration Options Note 1: The time period tPS is determined by the capacitor connected to PSAVE. Figure 1. 16-Bit Register Map for MAX4822 When CS is low (MAX4822/MAX4823 device is selected), data at DIN is clocked into the shift register synchronously with SCLK's rising edge. Driving CS from low to high latches the data in the shift register (Figures 5 and 6). DOUT is the output of the shift register. Data appears on DOUT synchronously with SCLK's falling edge and is identical to the data at DIN delayed by eight clock cycles for the MAX4823, or 16 clock cycles for the MAX4822. When shifting the input data, A7 is the first input bit in and out of the shift register for the MAX4822 device. D7 is the first bit in or out of the shift register for 10 ______________________________________________________________________________________ +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode MAX4822-MAX4825 MSB D7 OUT8 D6 OUT7 D5 OUT6 D4 OUT5 D3 OUT4 D2 OUT3 D1 OUT2 LSB D0 OUT1 A2 Low Low Low Low High High High High A1 Low Low High High Low Low High High A0 Low High Low High Low High Low High OUTPUT OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 Note: Setting DN to logic 1 turns on output OUTN+1. Setting DN to logic 0 turns off output OUTN+1. Example: Setting the D2 = 1 turns OUT3 on. Figure 2. 8-Bit Register Map for MAX4823 Figure 3. Register Address Map for MAX4824/MAX4825 CS tCSS SCLK tDH tDS DIN D7 D6 D1 tDO DOUT tON, tOFF OUT_ D0 tCL tCH tCSH tCSW Figure 4. 3-Wire Serial-Interface Timing Diagram the MAX4823 device. If the address A0.......A7 is not 00h or 01h, then the outputs and the PSAVE configuration register are not updated. The address is stored in the shift register only. While CS is low, the OUT_ outputs always remain in their previous state. For the MAX4823, drive CS high after 8 bits of data have been shifted in to update the output state of the MAX4823, and to further inhibit data from entering the shift register. For the MAX4822, drive CS high after 16 bits of data have been shifted in to update the output state of the MAX4822, and to further inhibit data from entering the shift register. When CS is high, transitions at DIN and SCLK have no effect on the output, and the first input bit A7 (or D7) is present at DOUT. For the MAX4822, if the number of data bits entered while CS is low is greater or less than 16, the shift register contains only the last 16 bits, regardless of when they were entered. For the MAX4823, if the number of data bits entered while CS is low is greater or less than 8, the shift register contains only the last 8 data bits, regardless of when they were entered. Parallel Interface (MAX4824/MAX4825) The parallel interface consists of 3 address bits (A0, A1, A2) and one level selector bit (LVL). The address bits determine which output is updated, and the level bit determines whether the addressed output is switched on (LVL = high) or off (LVL = low). When CS is high, the address and level bits have no effect on the state of the outputs. Driving CS from low to high latches 11 ______________________________________________________________________________________ +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode MAX4822-MAX4825 CS SCLK DIN A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 5. 3-Wire Serial-Interface Operation for MAX4822 level data to the parallel register and updates the state of the outputs. Address data entered after CS is pulled low is not reflected in the state of the outputs following the next low-to-high transition on CS (Figure 7). SET/RESET Functions The MAX4822-MAX4825 feature set and reset inputs that allow simultaneous turn-on or turn-off of all outputs using a single control line. Drive SET low to set all latches and registers to 1 and turn all outputs on. SET overrides all serial/parallel control inputs. Drive RESET low to clear all latches and registers and to turn all outputs off. RESET overrides all other inputs including SET. the CS input to address one device at a time. Drive CS low to select a slave and input the data into the shift register. Drive CS high to latch the data and turn on the appropriate outputs. Typically, in this configuration only one slave is addressed at a time. Power-Save Mode The MAX4822/MAX4824 feature a unique power-save mode where the relay current, after activation, can be reduced to a level just above the relay hold-current threshold. This mode keeps the relay activated while significantly reducing the power consumption. In serial mode (MAX4822), choose between seven current levels ranging from 30% to 90% of the nominal current in 10% increments. The actual percentage is determined by the power-save configuration register (Figure 1). In parallel mode (MAX4824), the power-save current is fixed at 60% of the nominal current. Power-Save Timer Every time there is a write operation to the device (CS transitions from low to high), the MAX4822/MAX4824 start charging the capacitor connected to PSAVE. The serial power-save implementation is such that a write operation does not change the state of channels already in power-save mode (unless the write turns the channel OFF). After a certain time period, t PS (determined by the capacitor value), the capacitor reaches a voltage threshold that sets all active outputs to power-save mode. The tPS period should be made long enough to allow the relay to turn on completely. The time period tPS can be adjusted by using different capacitor values Power-On Reset The MAX4822-MAX4825 feature power-on reset. The power-on reset function causes all latches to be cleared automatically upon power-up. This ensures that all outputs come up in the off or high-impedance state. Applications Information Daisy Chaining The MAX4822/MAX4823 feature a digital output (DOUT) that provides a simple way to daisy chain multiple devices. This feature allows driving large banks of relays using only a single serial interface. To daisy chain multiple devices, connect all CS inputs together, and connect the DOUT of one device to the DIN of another device (see Figure 8). During operation, a stream of serial data is shifted through the MAX4822/ MAX4823 devices in series. When CS goes high, all outputs update simultaneously. The MAX4822/MAX4823 can also be used in a slave configuration that allows individual addressing of devices. Connect all the DIN inputs together, and use 12 ______________________________________________________________________________________ +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode connected to PSAVE. The value tPS is given by the following formula: tPS = 32 x C where C is in F and tPS is in ms. For example, if the desired t PS is 20ms, then the required capacitor value is 20 / 32 = 0.625F. Power-Save Mode Accuracy The current through the relay is controlled by setting the voltage at OUT_ to a percentage of the VCC supply as specified under the Electrical Characteristics and in the register description. The current through the relay (IOUT) depends on the switch on-resistance, RON, in addition to the relay resistance RR according to the following relation: IOUT = VCC / (RON + RR) The power-save, current-setting I PS depends on the fraction of the supply voltage VCC that is set by the loop depending on the following relation: IPS = VCC - ( x VCC) / RR Therefore: IPS / IOUT = (1- ) x (1 + RON / RR) This relation shows how the fraction of reduction in the current depends on the switch on-resistance, as well as from the accuracy of the voltage setting (). The higher the RON with respect to RR, the higher the inaccuracy. This is particularly true at low voltage when the relay resistance is low (less than 40) and the switch can account for up to 10% of the total resistance. In addition, when the supply-voltage setting () is low (10% or 20%) and the supply voltage (VCC) is low, the voltage drop across the switch (I OUT x R ON ) may already exceed, or may be very close to, the desired voltagesetting value. tLS LVL tON, tOFF VOUT MAX4822-MAX4825 CS SCLK DIN D7 D6 D5 D4 D3 D2 D1 D0 Figure 6. 3-Wire Serial-Interface Operation for the MAX4823 CS tAS A_ tAH tLH Figure 7. Parallel-Interface Timing Diagram Daisy Chaining and Power-Save Mode In a normal configuration using the power-save feature, several MAX4822s can be daisy chained as shown in Figure 9. For each MAX4822, the power-save timing tPD (time it takes to reduce the relay current once the relay is actuated) is controlled by the capacitor connected to PSAVE. An alternative configuration that eliminates the PSAVE capacitors uses a common PSAVE control line driven by an open-drain n-channel MOSFET (Figure 10). In this configuration, the PSAVE inputs are connected together to asynchronously control the power-save timing for all the MAX4822s in the chain. The C/P drives the n-channel MOSFET low for the duration of a write cycle to the SPI chain, plus some delay time to allow the relays to close. (This time is typically specified in the relay data sheet.) Once this delay time has elapsed, the n-channel MOSFET is turned off, allowing the MAX4822's internal 35A pullup current to raise PSAVE to a logic-high level, activating the power-save mode in all active outputs. MOSFET Selection In the daisy-chain configuration of Figure 10, the n-channel MOSFET drives PSAVE low. When the n-channel MOSFET is turned off, PSAVE is pulled high by an internal 35A pullup in each MAX4822, and the power-save mode is enabled. Because of the paralleled PSAVE pullup currents, the required size of the n-channel MOSFET depends upon the number of MAX4822 devices in the chain. Determine the size of the n-channel MOSFET by the following relation: RON < 1428 / N ______________________________________________________________________________________ 13 +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode MAX4822-MAX4825 VCC 0.1F VCC 0.1F VCC 0.1F VCC DIN DIN DOUT DIN VCC DOUT DIN VCC DOUT MAX4823 OUT1 SCLK SCLK CS GND SCLK SCLK CS MAX4823 OUT1 SCLK SCLK CS MAX4823 OUT1 OUT8 PGND OUT8 GND PGND OUT8 GND PGND CS Figure 8. Daisy-Chain Configuration VCC 0.1F VCC 0.1F VCC 0.1F VCC DIN DIN DOUT DIN VCC DOUT DIN VCC DOUT MAX4822 OUT1 PSAVE 0.47F SCLK CS GND OUT8 PGND 0.47F PSAVE SCLK CS MAX4822 OUT1 0.47F PSAVE SCLK CS MAX4822 OUT1 OUT8 GND PGND OUT8 GND PGND SCLK CS Figure 9. Daisy-Chained MAX4822s with a Capacitor Connected to PSAVE where N is the total number of MAX4822 devices in a single chain, and R ON is the on-resistance of the n-channel MOSFET in s. For example, if N = 10: RON < 142 An n-channel MOSFET with R ON less than 142 is required for a daisy chain of 10 MAX4822 devices. Inductive Kickback Protection with Fast Recovery Time The MAX4822-MAX4825 feature built-in inductive kickback protection to reduce the voltage spike on OUT_ generated by a relay's coil inductance when the output is suddenly switched off. An internal Zener clamp allows the inductor current to flow back to ground. The Zener configuration significantly reduces the recovery time (time it takes to turn off the relay) when compared to protection configurations with just one diode across the coil. 14 ______________________________________________________________________________________ +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode MAX4822-MAX4825 VCC 0.1F VCC 0.1F VCC 0.1F VCC DIN DIN DOUT DIN VCC DOUT DIN VCC DOUT MAX4822 OUT1 PSAVE SCLK VCC CS GND OUT8 PGND PSAVE SCLK CS MAX4822 OUT1 PSAVE SCLK CS MAX4822 OUT1 OUT8 GND PGND OUT8 GND PGND N SCLK CS Figure 10. Daisy-Chaining MAX4822s with a PSAVE Connected to an n-Channel MOSFET Chip Information TRANSISTOR COUNT: 5799 PROCESS: BiCMOS ______________________________________________________________________________________ 15 +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode MAX4822-MAX4825 MAX4822/MAX4823 Functional Diagram (Serial Interface) OUT1 VCC POWERON RESET POWER-SAVE CONFIGURATION REGISTER OUT2 OUT3 PSAVE OUT4 OUT5 OUT6 ON1 CONTROL ON2 REGISTER ON3 ON4 ON5 ON6 ON7 ON8 OUT7 OUT8 MAX4822 MAX4823 RESET SET DIN SHIFT REGISTER DOUT SCLK CS PSAVE POWER SAVE GND MAX4822 ONLY PGND 16 ______________________________________________________________________________________ +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode MAX4824/MAX4825 Functional Diagram (Parallel Interface) MAX4822-MAX4825 OUT1 VCC OUT2 OUT3 PSAVEON/OFF OUT4 OUT5 OUT6 ON1 CONTROL ON2 REGISTER ON3 ON4 ON5 ON6 ON7 ON8 OUT7 OUT8 MAX4824 MAX4825 RESET SET LVL A2 A1 A0 4-TO-8 DECODER CS PSAVE POWER SAVE GND MAX4824 ONLY PGND ______________________________________________________________________________________ 17 +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode MAX4822-MAX4825 Pin Configurations TOP VIEW PGND PGND OUT1 OUT1 18 OUT2 20 19 18 17 16 20 19 17 OUT2 VCC VCC SET SET RESET CS DIN SCLK DOUT 1 2 3 4 5 10 6 7 8 9 15 14 OUT3 OUT4 PSAVE OUT5 OUT6 RESET CS DIN SCLK DOUT 1 2 3 4 5 10 6 7 8 9 16 15 14 OUT3 OUT4 N.C. OUT5 OUT6 MAX4822 13 12 11 MAX4823 13 12 11 N.C. OUT8 OUT7 N.C. OUT8 PGND OUT7 17 OUT2 GND GND THIN QFN THIN QFN PGND 20 19 18 17 16 20 19 18 RESET CS LVL A0 A1 1 2 3 4 5 10 6 7 8 9 15 14 OUT3 OUT4 PSAVE OUT5 OUT6 RESET CS LVL A0 A1 1 2 3 4 5 10 6 7 8 9 16 PGND OUT1 OUT1 OUT2 VCC VCC SET SET PGND 15 14 OUT3 OUT4 N.C. OUT5 OUT6 MAX4824 13 12 11 MAX4825 13 12 11 A2 OUT8 OUT7 A2 OUT8 PGND OUT7 GND GND THIN QFN THIN QFN 18 ______________________________________________________________________________________ PGND +3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save Mode Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS MAX4822-MAX4825 MAX4822-MAX4825 PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 E 1 2 PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. |
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